The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for even smaller electronic devices has grown recently, there has grown a need for smaller and more creative packaging techniques of semiconductor dies.
As semiconductor technologies evolve, three dimensional integrated circuits have emerged as an effective alternative to further reduce the physical size of a semiconductor chip. In a three dimensional integrated circuit, active circuits such as logic, memory, processor circuits and the like are fabricated on different wafers and each wafer die is stacked on top of a packaging component using pick-and-place techniques. Through silicon vias provide connections between different wafers stacked together. Much higher density can be achieved by employing three dimensional integrated circuits. In sum, three dimensional integrated circuits can achieve smaller form factors, cost-effectiveness, increased performance and lower power consumption.
Through silicon vias in three dimensional integrated circuits may be fabricated by suitable techniques. For example, an opening may be formed on a first side (e.g., the active side) of a substrate. The bottom of the opening is deeper than active circuits of the substrate. Conductive materials such as copper may be filled in the opening. Then, a thinning process is performed on a second side (e.g., the backside) of the substrate until the conductive material is exposed. As such, a through silicon via is formed. One advantageous feature of three dimensional integrated circuits is that parasitic losses are reduced by employing through silicon vias.
Due to the mismatch between the coefficient of thermal expansion (CTE) of copper and the CTE of silicon, there may be a concentration of stress in the areas adjacent to a through silicon via opening. Such a concentration of stress may lead to reliability problems such as cracking. In addition, the through silicon via induced stress may cause performance degradation if active circuits such as transistors are formed in the adjacent areas of the through silicon via opening. In order to obtain reliable and high performance transistors, the area adjacent to a through silicon via is defined as a keep-out zone for active circuits. There is a need to reduce the size of the keep-out zone so that the active circuit density of a wafer may be increased as a result.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.